Development of Low-Power VLSI Architectures for Next-Generation Computing
Author(s): Veena C. Tyagi¹, Roopa Bansal², Kiran Pathak³
Affiliation: 1,2,3Department of Electrical and Electronics Engineering, Skyline Institute of Engineering and Technology, Greater Noida, Uttar Pradesh, India
Page No: 6-10-
Volume issue & Publishing Year: Volume 2 Issue3, March-2025
Journal: International Journal of Modern Engineering and Management | IJMEM
ISSN NO: 3048-8230
DOI:
Abstract:
The demand for high-performance computing has grown exponentially with the rise of artificial intelligence, cloud computing, and Internet of Things (IoT) applications. However, the corresponding increase in power consumption poses a significant challenge for very-large-scale integration (VLSI) design. Low-power VLSI architectures are critical for enhancing energy efficiency without compromising computational throughput. This paper explores the design methodologies, circuit-level techniques, and system-level innovations that enable the development of energy-efficient VLSI architectures for next-generation computing. Techniques such as clock gating, power gating, multi-threshold CMOS, approximate computing, and near-threshold voltage operation are analyzed in detail. Experimental studies indicate that integrating these methods in multi-core and AI accelerators reduces power consumption by 35–50% while maintaining acceptable performance levels. The study highlights the importance of balancing trade-offs between performance, area, and energy efficiency for sustainable computing systems.
Keywords:
VLSI, Low-Power Design, Multi-Threshold CMOS, Approximate Computing, Next-Generation Computing
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